Hans Wu, Taipei; Esther Lam, DIGITIMES [Friday 2 November 2007]
While having said that loss is inevitable for the entire DRAM industry in 2007, Powerchip Semiconductor Corporation (PSC), in contrast to its Taiwan-based rivals, is striving to swing from loss by guiding a 15-20% on-quarter cost down along with its ramp up of 70nm wafer starts, said company executives during a recent investors conference.
Frank Huang, chairman at PSC, guided that the company will have 75% of its wafer starts at 70nm in the fourth quarter of 2007, translating to fabricating about half of its 12-inch wafer output at the 70nm node. Alongside the migration to 70nm, final wafer starts at 90nm are scheduled in January 2008. The technology node conversion is expected to reward PSC with a 15-20% reduction in DRAM production costs.
Technology conversion to 70nm from 90nm will deliver a US$600 per wafer cost reduction, Huang highlighted. PSC will be able to produces about 1,416 DDR2 dies in 512Mb out of a 70nm-made wafer at a yield rate of 85%, versus the 908 dies as from 90nm, a difference of over 400 extra dies between the two nodes. Yields for 512Mb DDR2 have already reached 85% and the company expects to hit 85-88% for 1Gb components during year-end of 2007, said company president Brian Hsieh. Further technology node shrinks are planned for 2008. PSC said it will introduce wafer starts at 60nm in the second quarter of 2008 with production to ramp up in the third quarter.
Huang emphasized that PSC should have seen its gross margin hit bottom during September and October. Noting that persistent DRAM downward trends usually last for 7-8 months, he said expects a price rebound to arrive in March 2008 with 512Mb DDR2 price likely to resume to US$2-2.50 levels.
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